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ISL62381, ISL62382, ISL62383
Data Sheet August 7, 2008 FN6665.4
High-Efficiency, Quad or Triple-Output System Power Supply Controller for Notebook Computers
The ISL62381, ISL62382, ISL62383 family of controllers generate supply voltages for battery-powered systems. The ISL62381 and ISL62382 include two pulse-width modulation (PWM) controllers, adjustable from 0.6V to 5.5V, and two linear regulators, LDO5 and LDO3, that generate a fixed 5V and an adjustable output respectively, and each can deliver up to 100mA. The ISL62383 has the same outputs as the ISL62381 and ISL62382, but without LDO3 linear regulator. The channel 2 switching regulator will automatically take over the LDO5 load when programmed to 5V output. This provides a large power savings and boosts efficiency. The ISL62381, ISL62382, ISL62383 family include on-board power-up sequencing, two power-good (PGOOD) outputs, digital soft-start, and internal soft-stop output discharge that prevent negative voltages on shutdown. The patented R3 PWM control scheme provides a low jitter system with fast response to load transients. Light-load efficiency is improved with period-stretching discontinuous conduction mode (DCM) operation. To eliminate noise in audio frequency applications, an ultrasonic DCM mode is included, which limits the minimum switching frequency to approximately 28kHz. The ISL62381, ISL62382, is available in 32 Ld 5x5 TQFN package, and ISL62383 is available in 28 Ld 4x4 TQFN package. ISL62381, ISL62382, ISL62383 family can operate over the extended temperature range (-10C to +100C).
Features
* High Performance R3 Technology * Fast Transient Response * 1% Output Voltage Accuracy: -10C to +100C * Two Fully Programmable Switch-Mode Power Supplies with Independent Operation * Programmable Switching Frequency * Integrated MOSFET Drivers and Bootstrap Diode * Adjustable (+1.2V to +5V) LDO Output * Fixed +5V LDO Output with Automatic Switchover to SMPS2 * Internal Soft-Start and Soft-Stop Output Discharge * Wide Input Voltage Range: +5.5V to +25V * Full and Ultrasonic Pulse-Skipping Mode * Power-Good Indicator * Overvoltage, Undervoltage and Overcurrent Protection * Fault Identification by PGOOD Pull-Down Resistance * Thermal Monitor and Protection * Pb-Free (RoHS Compliant)
Applications
* Notebook and Sub-Notebook Computers * PDAs and Mobile Communication Devices * 3-Cell and 4-Cell Li+ Battery-Powered Devices * General Purpose Switching Buck Regulators
Ordering Information
PART NUMBER (Note) PART MARKING TEMP RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
ISL62381HRTZ* 62381 HRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5A ISL62382HRTZ* 62382 HRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5A ISL62383HRTZ* 623 83HRTZ -10 to +100 28 Ld 4x4 TQFN L28.4x4 *Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL62381, ISL62382, ISL62383 Pinouts
ISL62381, ISL62382 (32 LD TQFN) TOP VIEW
OCSET2 PHASE2 UGATE2 BOOT2 VOUT2 VOUT2 ISEN2
ISL62383 (28 LD TQFN) TOP VIEW
PHASE2 23 OSCET2 UGATE2 22 21 20 19 GND 18 17 16 15 8 FB1 9 VOUT1 10 ISEN1 11 OCSET1 12 EN1 13 PHASE1 14 UGATE1 BOOT2 LGATE2 PGND LDO5 VIN LGATE1 BOOT1 ISEN2 EN2 24
EN2
FB2
32 PGOOD2 FSET2 FCCM VCC2 VCC1 LDO3EN FSET1 PGOOD1 1 2 3 4
31
30
29
28
27
26
25 24 23 22 21 LGATE2 PGND LDO5 VIN LDO3IN LDO3 LDO3FB LGATE1 PGOOD2 FSET2 FCCM VCC2 VCC1 FSET1 PGOOD1 1 2 3 4 5 6 7
28
FB2
27
26
25
GND 5 6 7 8 9 FB1 10 VOUT1 11 ISEN1 12 OSCET1 13 EN1 14 PHASE1 15 UGATE1 16 BOOT1 20 19 18 17
2
FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383
Absolute Maximum Ratings
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VCC1,2, PGOOD1,2, LDO5 to GND. . . . . . . . . . . . . . -0.3V to +7.0V EN1,2, LDO3EN . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC1 + 0.3V VOUT1,2, FB1,2, LDO3FB, FSET1,2 . . -0.3V to GND, VCC1 + 0.3V PHASE1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V (<100ns Pulse Width, 10J) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V BOOT1,2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V BOOT1,2 to PHASE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V UGATE1,2 . . . . . . . . . . . (DC) -0.3V to PHASE1,2, BOOT1,2 + 0.3V (<200ns Pulse Width, 20J) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V LGATE1,2 . . . . . . . . . . . . . . . . . . . (DC) -0.3V to GND, VCC1 + 0.3V (<100ns Pulse Width, 4J) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V LDO3, LDO5 Output Continuous Current . . . . . . . . . . . . . . +100mA
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) TQFN Package . . . . . . . . . . . . . . . . . . 40 3 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -10C to 100C Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . 5.5V to 25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. Limits established by characterization and are not production tested. 4. FSW accuracy reflects IC tolerance only; it does not include frequency variation due to VIN, VOUT, LOUT, ESRCOUT, or other application specific parameters.
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise noted. Typical values are at TA = +25C, VIN = 12V; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested CONDITIONS MIN TYP MAX UNITS
PARAMETER VIN VIN Power-on Reset (POR) Rising Threshold Hysteresis VIN Shutdown Supply Current VIN Standby Supply Current LINEAR REGULATOR LDO5 Output Voltage I_LDO5 = 0
5.3 20 -
5.4 80 6 150
5.5 150 15 250
V mV A A
EN1 = EN2 = GND or Floating, LDO3EN = GND EN1 = EN2 = GND or Floating, LDO3EN = VCC1
4.9 4.9 4.63 -
5.0 5.0 190 4.35 4.15 4.80 2.5 1.2 180 -
5.1 5.1 4.93 3.2 5 2.5 1.06 1
V V mA V V V V V mA V V A
I_LDO5 = 100mA (Note 3) LDO5 Short-Circuit Current (Note 3) LDO5 UVLO Threshold Voltage (Note 3) LDO5 = GND Rising edge of LDO5 Falling edge of LDO5 SMPS2 to LDO5 Switchover Threshold SMPS2 to LDO5 Switchover Resistance (Note 3) VOUT2 to LDO5, VOUT2 = 5V LDO3 Reference Voltage (Note 3) LDO3 Voltage Regulation Range LDO3 Short-Circuit Current (Note 3) LDO3EN Input Voltage LDO3IN > VLDO3+dropout LDO3 = GND Rising edge Falling edge LDO3EN Input Leakage Current LDO3 Discharge ON-Resistance LDO3EN = GND or VCC1 LDO3EN = GND
1.2 1.1 0.94 -1 -
36
60
3
FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise noted. Typical values are at TA = +25C, VIN = 12V; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested (Continued) CONDITIONS MIN TYP MAX UNITS
PARAMETER VCC VCC Input Bias Current (Note 3) VCC2 POR Threshold
EN1 = EN2 = VCC1, FB1 = FB2 = 0.65V Rising edge Falling edge
4.35 4.10
2 4.45 4.20
4.55 4.30
mA V V
PWM Reference Voltage (Note 3) Regulation Accuracy FB Input Bias Current Frequency Range Frequency Set Accuracy (Note 4) VOUT Voltage Regulation Range VOUT Soft-Discharge Resistance POWER-GOOD PGOOD Pull-Down Impedance Soft-start, I_PGOOD = 5mA sinking UVP, I_PGOOD = 5mA sinking OVP, I_PGOOD = 5mA sinking OCP, I_PGOOD = 5mA sinking PGOOD Leakage Current Maximum PGOOD Sink Current (Note 3) PGOOD Soft-start Delay From EN high to PGOOD high (for one SMPS channel) EN2(1) = Floating, from EN1(2) high to PGOOD2(1) high GATE DRIVER UGATE Pull-Up ON-Resistance (Note 3) UGATE Source Current (Note 3) UGATE Pull-Down ON-Resistance (Note 3) UGATE Sink Current (Note 3) LGATE Pull-Up ON-Resistance (Note3) LGATE Source Current (Note3) LGATE Pull-Down ON-Resistance (Note 3) LGATE Sink Current (Note 3) UGATE to LGATE Deadtime (Note 3) LGATE to UGATE Deadtime (Note 3) Bootstrap Diode Forward Voltage (Note 3) Bootstrap Diode Reverse Leakage Current 200mA source current UGATE-PHASE = 2.5V 250mA source current UGATE-PHASE = 2.5V 250mA source current LGATE-PGND = 2.5V 250mA source current LGATE-PGND = 2.5V UG falling to LG rising, no load LG falling to UG rising, no load 2mA forward diode current VR = 25V 1.0 2.0 1.0 2.0 1.0 2.0 0.5 4.0 21 21 0.58 0.2 1.5 1.5 1.5 0.9 1 A A A A ns ns V A PGOOD = VCC1 2.20 4.50 32 95 63 32 0 5 2.75 5.60 100 200 150 100 1 3.70 7.50 A mA ms ms FSW = 300kHz VIN > 6V for VOUT = 5.5V VOUT regulated to 0.6V FB = 0.6V -1 -10 200 -12 0.6 0.6 14 1 30 600 12 5.5 50 V % nA kHz % V
4
FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise noted. Typical values are at TA = +25C, VIN = 12V; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested (Continued) CONDITIONS MIN TYP MAX UNITS
PARAMETER CONTROL FCCM Input Voltage
Low level (DCM enabled) Float level (DCM with audio filter) High level (Forced CCM)
1.9 2.4 -2 1.9 2.4 -3.5 -
28 600 0.1
0.8 2.1 2 0.8 2.1 3.5 -
V V V A KHz V V V A k A
FCCM Input Leakage Current Audio Filter Switching Frequency (Note 3) EN Input Voltage
FCCM = GND or VCC1 FCCM floating Clear fault level/SMPS OFF level Delay start level SMPS ON level
EN Input Leakage Current ISEN Input Impedance (Note 3) ISEN Input Leakage Current (Note 3) PROTECTION OCSET Input Impedance (Note 3) OCSET Input Leakage Current (Note 3) OCSET Current Source OCP (VOCSET-VISEN) Threshold UVP Threshold OVP Threshold
EN = GND or VCC1 EN = VCC1 EN = GND
EN = VCC1 EN = GND EN = VCC1
9 -1.75
600 0.1 10.0 0.0 84 116 103 150 135
10.5 1.75 87 120 106 -
k A A mV % % % C C
Falling edge, referenced to FB Rising edge, referenced to FB Falling edge, referenced to FB
81 113 99.5 -
OTP Threshold (Note 3)
Rising edge Falling edge
5
FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383 Typical Application Circuits
VBAT 4x10F 0.22F 3 .3 V 330F 4.7H IRF7821
UGATE1 PHASE1 UGATE2 PHASE2 BO O T1 V IN BO O T2
The below typical application circuits generate the 5V/8A and 3.3V/8A main supplies in a notebook computer. The input supply (VBAT) range is 5.5V to 25V
0.22F IRF7821 4.7H 5V 330F
0.022F 14k IRF7832 14k
LG ATE1 LGATE2
14k IRF7832
0.022F
ISL62381, ISL62382, ISL62383
OCSET1 OCSET2 IS E N 2 VOUT2 FB2 L D O 3 IN * IS E N 1 VOUT1 FB1
750 45.3k 1200pF
14k 68.1k
750 1200pF
3 .3 V 10k 4.7F
LDO 3*
9.09k 100k
17.4k
LDO 3FB* PGOOD1 PGOOD2 LDO5 EN1 EN2 LDO 3EN * VCC1 FCCM FSET1 FSET2 GND
5V 4.7F
10k 10
100k
LDO5
1F
1F
VCC2 PGND
24.3k 19.6k 0.01F
0.01F
*ISL62381, ISL62382 ONLY
FIGURE 1. TYPICAL APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
VBAT
4x10F 0.22F IRF7821
UGATE1 PHASE1 UGATE2 PHASE2 BOOT1 V IN BOOT2
IRF7821
0.22F 4.7H 0.001
3 .3 V
330F 0.001 1k
4.7H 1k IRF7832
5V
330F
IRF7832
LG ATE1 LG ATE2
1k
1k 750
ISL62381, ISL62382, ISL62383
750 1200pF 45.3k
OCSET1 IS E N 1 VOUT1 FB1 OCSET2 IS E N 2 VOUT2 FB2 L D O 3 IN *
68.1k
1200pF
3 .3 V
LDO 3*
9.09K 100k
10k
4.7F
17.4k
LDO 3FB* PGOOD1 PGOOD2 LDO 5 EN1 EN2 LD O 3EN* VCC1 VCC2 FCCM FSET1 FSET2 GND
5V
4.7F
10k 10
100k
LDO5
1F
1F
PGND
24.3k 19.6k 0.01F
0.01F
*ISL62381, ISL62382 ONLY
FIGURE 2. TYPICAL APPLICATION CIRCUIT WITH RESISTOR CURRENT SENSE
6
FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383 Typical Application Circuits
VBAT
The below typical application circuits generate the 1.05V/15A and 1.5V/15A main supplies in a notebook computer. The input supply (VBAT) range is 5.5V to 25V
6x10F 0.22F
1 .0 5 V
BO O T1
IRF7821x2
V IN
BO O T2
0.22F
IRF7821x2
2.2H
UGATE1 PHASE1
UGATE2 PHASE2
2.2H
1 .5 V
330Fx2
0.022F 16.2k
LG ATE1
IRF7832x2
16.2k
LGATE2
IRF7832x2
0.022F
330Fx2
ISL62381, ISL62382, ISL62383
OCSET1 IS E N 1 VOUT1 FB1 OCSET2 IS E N 2 VOUT2 FB2 L D O 3 IN * PGOOD1 PGOOD2 LDO5 EN1 EN2 LDO 3EN * VCC1 FCCM FSET1 FSET2 GND
590 36.5K 1800pF
16.2k
16.2k 36.5k
590 1800pF
48.7k
3 .3 V LDO 3*
VBAT
24.3k
4.7F
17.4k
LDO 3FB* 5V
100k
LDO5
10K 10
100k
4.7F
1F *ISL62381, ISL62382 ONLY
1F
VCC2 PGND
17.4k 14k 0.01F
0.01F
FIGURE 3. TYPICAL APPLICATION CIRCUIT WITH INDUCTOR DCR CURRENT SENSE
VBAT
IRF7821x2
6x10F 0.22F
1 .0 5 V
BO O T1
V IN
IRF7821x2
BOOT2
0.22F
UGATE1 PHASE1 UG ATE2 PHASE2
IRF7832x2
2.2H 0.001 2k 2k
IRF7832x2
2.2H
0.001
1 .5 V
330Fx2
330Fx2 2k 2k 590
LG ATE1
LG ATE2
ISL62381, ISL62382, ISL62383
590 1800pF 36.5k
O CSET1 IS E N 1 VOUT1 FB1 3 .3 V LDO 3* L D O 3 IN * PGOOD1 PGOOD2 LDO5 EN1 EN2 LDO 3EN * VCC1 VCC2 FCCM FSET1 FSET2 GND OCSET2 IS E N 2 VOUT2 FB2 VBAT
36.5k
1800pF
24.3k
48.7k
4.7F
5V
17.4k
LDO 3FB*
100k
LDO5
10k 10
100k
4.7F
1F
1F
PGND
17.4k 14k 0.01F
0.01F
*ISL62381, ISL62382 ONLY
FIGURE 4. TYPICAL APPLICATION CIRCUIT WITH RESISTOR CURRENT SENSE
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FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383 Pin Descriptions
PIN NUMBER 28 LD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 32 LD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME FUNCTION
PGOOD2 SMPS2 open-drain power-good status output. Connect to LDO5 through a 100k resistor. Output will be high when the SMPS2 output is within the regulation window with no faults detected. FSET2 FCCM VCC2 VCC1 Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage. Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation. SMPS2 analog power supply input for reference voltages and currents. Connect to VCC1 with a 10 resistor. Bypass to ground with a 1F ceramic capacitor near the IC. SMPS1 analog power supply input for reference voltages and currents. It is internally connected to the LDO5 output. Bypass to ground with a 1F ceramic capacitor near the IC.
LDO3EN Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input. FSET1 Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. A small ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage.
PGOOD1 SMPS1 open-drain power-good status output. Connect to LDO5 through a 100k resistor. Output will be high when the SMPS1 output is within the regulation window with no faults detected. FB1 VOUT1 ISEN1 SMPS1 feedback input used for output voltage programming and regulation. SMPS1 output voltage sense input. Used for soft-discharge. SMPS1 current sense input. Used for ove-current protection and R3 regulation.
OCSET1 Input from current-sensing network used to program the overcurrent shutdown threshold for SMPS1. EN1 Logic input to enable and disable SMPS1. A logic high will enable SMPS1 immediately. A logic low will disable SMPS1. Floating this input will delay SMPS1 start-up until after SMPS2 achieves regulation.
PHASE1 SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the synchronous NMOS drain, and the output inductor for SMPS1. UGATE1 High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET. BOOT1 LGATE1 SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to PHASE1 with a 0.22F ceramic capacitor. Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
LDO3FB LDO3 linear regulator feedback input used for output voltage programming and regulation. LDO3 LDO3IN VIN LDO5 PGND LGATE2 BOOT2 LDO3 linear regulator output, providing up to 100mA. Bypass to ground with a 4.7F ceramic capacitor. Power input for LDO3. Must be connected to a voltage greater than the LDO3 set point plus the dropout voltage. Feed-forward input for line voltage transient compensation. Connect to the power train input voltage. 5V linear regulator output, providing up to 100mA before switchover to SMPS2. Bypass to ground with a 4.7F ceramic capacitor. Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents. Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET. SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to PHASE2 with a 0.22F ceramic capacitor.
UGATE2 High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET. PHASE2 SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS source, the synchronous NMOS drain, and the output inductor for SMPS2. EN2 Logic input to enable and disable SMPS2. A logic high will enable SMPS2 immediately. A logic low will disable SMPS2. Floating this input will delay SMPS2 start-up until after SMPS1 achieves regulation.
OCSET2 Input from current-sensing network used to program the over-current shutdown threshold for SMPS2. ISEN2 VOUT2 SMPS2 current sense input. Used for overcurrent protection and R3 regulation. SMPS2 output voltage sense input. Used for soft-discharge and switchover to LDO5 output.
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FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383 Pin Descriptions (Continued)
PIN NUMBER 28 LD 28 Bottom Pad 32 LD 32 Bottom Pad NAME FB2 GND FUNCTION SMPS2 feedback input used for output voltage programming and regulation. Analog ground of the IC. Unless otherwise stated, signals are reference to this GND.
Typical Performance
100 95 90 EFFICIENCY (%) EFFICIENCY (%) 85 80 75 70 65 60 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 100
VIN = 7V
95 90
VIN = 12V VIN = 19V
85 80 75 70 65 60 0.5 1.5 2.5 3.5
VIN = 12V VIN = 19V
VIN = 7V
4.5
5.5
6.5
7.5
8.5
IOUT (A)
IOUT (A)
FIGURE 5. CHANNEL 1 EFFICIENCY AT VO = 3.3V
FIGURE 6. CHANNEL 2 EFFICIENCY AT VO = 5V
VO1
VO1
FB1
FB1
PGOOD1 PGOOD1
PHASE1
PHASE1
FIGURE 7. POWER-ON, VIN = 12V, LOAD = 5A, VO = 3.3V
FIGURE 8. POWER-OFF, VIN = 12V, IO = 5A, VO = 3.3V
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FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383 Typical Performance (Continued)
VO1
VO1
FB1 FB1
PGOOD1
PGOOD1
EN1 EN1
FIGURE 9. ENABLE CONTROL, EN1 = HIGH, VIN = 12V, VO = 3.3V, IO = 5A
FIGURE 10. ENABLE CONTROL, EN1 = LOW, VIN = 12V, VO = 3.3V, IO = 5A
VO1 PHASE1
VO1
PHASE1
VO2 PHASE2
VO2
PHASE2
FIGURE 11. CCM STEADY-STATE OPERATION,VIN = 12V, VO1 = 3.3V, IO1 = 5A, VO2 = 5V, IO2 = 5A
FIGURE 12. DCM STEADY-STATE OPERATION,VIN = 12V, VO1 = 3.3V, IO1 = 0. 2A, VO2 = 5V, IO2 = 0. 2A
VO1
VO1
PHASE1 PHASE1 VO2 PHASE2
IO1
FIGURE 13. AUDIO FILTER OPERATION, VIN = 12V, VO1 = 3.3V, VO2 = 5V, NO LOAD
FIGURE 14. TRANSIENT RESPONSE, VIN = 12V, VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/s
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FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383 Typical Performance (Continued)
VO1 VO1
PHASE1
PHASE1
IO1
IO1
FIGURE 15. LOAD INSERTION RESPONSE, VIN = 12V, VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/s
FIGURE 16. LOAD RELEASE RESPONSE, VIN = 12V, VO = 3.3V, IO = 0.1A/8.1A @ 2.5A/s
EN1
EN2
VO1
VO1
VO2
VO2
FIGURE 17. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V, EN2 = FLOAT, NO LOAD
FIGURE 18. DELAYED START, VIN = 12V, VO1 = 3.3V, VO2 = 5V, EN1 = FLOAT, NO LOAD
VO1
VO1
PGOOD1
PGOOD1
VO2
IO1
PGOOD2
FIGURE 19. DELAYED START , VIN = 12V, VO1 = 3.3V, VO2 = 5V, EN1 = 1, EN2 = FLOAT, NO LOAD
FIGURE 20. OVERCURRENT PROTECTION, VIN = 12V, VO = 3.3V
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FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383 Typical Performance (Continued)
VO1 VO1
UGATE1-PHASE1
UGATE1-PHASE1
LGATE1
LGATE1
PGOOD1
PGOOD1
FIGURE 21. CROWBAR OVERVOLTAGE PROTECTION, VIN = 12V, VO = 3.3V, NO LOAD
FIGURE 22. TRI-STATE OVERVOLTAGE PROTECTION, VIN = 12V, VO = 3.3V, NO LOAD
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ISL62381, ISL62382, ISL62383 Block Diagram
VIN VOUT2
FSET1/2 4.8V 5V LDO R3 MODULATOR VREF 0.6V BOOT1/2 FCCM VOUT1/2 LDO5
FB1/2
PWM
UGATE DRIVER
UGATE1/2
PHASE1/2
SOFT DISCHARGE LGATE DRIVER LGATE1/2
PGND EN1
LDO3EN*
START-UP AND SHUTDOWN LOGIC
PGOOD1/2
VCC1/2
10A OCSET1/2 ISEN1/2 OCP PROTECTION LOGIC OVP/UVP/OCP/OTP
BIAS AND REFERENCE
T-PAD
LDO3IN* VREF + 16% UVP LDO3FB*
FB1/2 OVP VREF - 16% THERMAL MONITOR
3.3V LDO
LDO3*
SOFT DISCHARGE *ISL62381, ISL2382 ONLY
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ISL62381, ISL62382, ISL62383 Theory of Operation
Four Output Controller
The ISL62381 and ISL62382 generate four regulated output voltages, including two PWM controllers and two LDOs. The two PWM channels are identical and almost entirely independent, with the exception of sharing the GND pin. Unless otherwise stated, only one individual channel is discussed, and the conclusion applies to both channels. VCOMP and VCOMP + VW thresholds. The PWM switching frequency is proportional to the slew rates of the positive and negative slopes of VR; it is inversely proportional to the voltage between VW and VCOMP. Equation 3 illustrates how to calculate the window size based on output voltage and frequency set resistor RW.
V W = g m V OUT ( 1 - D ) R W (EQ. 3)
Programming the PWM Switching Frequency
The ISL62381, ISL62382, ISL62383 family does not use a clock signal to produce PWMs. The PWM switching frequency FSW is programmed by the resistor RW that is connected from the FSET pin to the GND pin. The approximate PWM switching frequency can be expressed as written inEquation 4:
1 F SW = -------------------------------10 C R R W (EQ. 4)
PWM Modulator
The ISL62381, ISL62382 and ISL62383 modulator features Intersil's R3 technology, a hybrid of fixed frequency PWM control and variable frequency hysteretic control. Intersil's R3 technology can simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The R3 modulator synthesizes an AC signal VR, which is an analog representation of the output inductor ripple current. The duty-cycle of VR is the result of charge and discharge current through a ripple capacitor CR. The current through CR is provided by a transconductance amplifier gm that measures the VIN and VO pin voltages. The positive slope of VR can be written as Equation 1:
V RPOS = g m ( V IN - V OUT ) C R (EQ. 1)
For a desired FSW, the RW can be selected by Equation 5.
1 R W = -----------------------------------10 C R F SW (EQ. 5)
where CR = 17pF with 20% error range. To smooth the FSET pin voltage, a ceramic capacitor such as 10nF is necessary to parallel with RW. It is recommended that whenever the control loop compensation network is modified, FSW should be checked for the correct frequency and if necessary, adjust RW .
The negative slope of VR can be written as Equation 2:
V RNEG = g m V OUT C R (EQ. 2)
Where gm is the gain of the transconductance amplifier.
WINDOW VOLTAGE VW (WRT VCOMP)
Power-On Reset
The ISL62381, ISL62382 and ISL62383 are disabled until the voltage at the VIN pin has increased above the rising power-on reset (POR) threshold voltage. The controller will be disabled when the voltage at the VIN pin decreases below the falling POR threshold. In addition to VIN POR, the LDO5 pin is also monitored. If its voltage falls below 4.2V, the SMPS outputs will be shut down. This ensures that there is sufficient BOOT voltage to enhance the upper MOSFET.
RIPPLE CAPACITOR VOLTAGE VR
ERROR AMPLIFIER VOLTAGE VCOMP
EN, Soft-Start and PGOOD
PWM
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
A window voltage VW is referenced with respect to the error amplifier output voltage VCOMP, creating an envelope into which the ripple voltage VR is compared. The amplitude of VW is set by a resistor connected across the FSET and GND pins. The VR, VCOMP, and VW signals feed into a window comparator in which VCOMP is the lower threshold voltage and VCOMP + VW is the higher threshold voltage. Figure 23 shows PWM pulses being generated as VR traverses the
The ISL62381, ISL62382 and ISL62383 use a digital soft-start circuit to ramp the output voltage of each SMPS to the programmed regulation setpoint at a predictable slew rate. The slew rate of the soft-start sequence has been selected to limit the in-rush current through the output capacitors as they charge to the desired regulation voltage. When the EN pins are pulled above their rising thresholds, the PGOOD Soft-Start Delay, tSS, starts and the output voltage begins to rise. The FB pin ramps to 0.6V in approximately 1.5ms and the PGOOD pin goes to high impedance approximately 1.25ms after the FB pin voltage reaches 0.6V.
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1.5ms tSOFTSTART
VOUT VCC and LDO5 EN FB PGOOD
2.75ms PGOOD Delay
FIGURE 24. SOFT-START SEQUENCE FOR ONE SMPS
The PGOOD pin indicates when the converter is capable of supplying regulated voltage. It is an undefined impedance if VIN is not above the rising POR threshold or below the POR falling threshold. When a fault is detected, the ISL62381, ISL62382 and ISL62383 will turn on the open-drain NMOS, which will pull PGOOD low with a nominal impedance of 63 or 95. This will flag the system that one of the output voltages is out of regulation. Separate enable pins allow for full soft-start sequencing. Because low shutdown quiescent current is necessary to prolong battery life in notebook applications, the LDO5 5V LDO is held off until any of the three enable signals (EN1, EN2 or LDO3EN) is pulled high. Soft-start of all outputs will only start until after LDO5 is above the 4.2V POR threshold. In addition to user-programmable sequencing, the ISL62381, ISL62382 and ISL62383 include a pre-programmed sequential SMPS soft-start feature. Table 1 shows the SMPS enable truth table.
TABLE 1. SMPS ENABLE SEQUENCE LOGIC EN1 0 0 Float Float 0 1 1 Float 1 EN2 0 Float 0 Float 1 0 1 1 Float START-UP SEQUENCE Both SMPS outputs OFF simultaneously Both SMPS outputs OFF simultaneously Both SMPS outputs OFF simultaneously Both SMPS outputs OFF simultaneously SMPS1 OFF, SMPS2 ON SMPS1 ON, SMPS2 OFF Both SMPS outputs ON simultaneously SMPS1 enables after SMPS2 is in regulation SMPS2 enables after SMPS1 is in regulation
to clamp the gate of the MOSFET below the VGS(th) at turnoff. The current transient through the gate at turn-off can be considerable because the gate charge of a low r DS(ON) MOSFET can be large. Adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver output has fallen below approximately 1V. The dead-time shown in Figure 25 is extended by the additional period that the falling gate voltage stays above the 1V threshold. The typical dead-time is 21ns. The high-side gate-driver output voltage is measured across the UGATE and PHASE pins while the low-side gate-driver output voltage is measured across the LGATE and PGND pins. The power for the LGATE gate-driver is sourced directly from the LDO5 pin. The power for the UGATE gate-driver is sourced from a "boot" capacitor connected across the BOOT and PHASE pins. The boot capacitor is charged from the 5V LDO5 supply through a "boot diode" each time the low-side MOSFET turns on, pulling the PHASE pin low. The ISL62381, ISL62382 and ISL62383 have integrated boot diodes connected from the LDO5 pins to BOOT pins.
tLGFUGR
tUGFLGR
50% UGATE LGATE 50%
FIGURE 25. LGATE AND UGATE DEAD-TIME
Diode Emulation
FCCM is a logic input that controls the power state of the ISL62381, ISL62382 and ISL62383. If forced high, the ISL62381, ISL62382 and ISL62383 will operate in forced continuous-conduction-mode (CCM) over the entire load range. This will produce the best transient response to all load conditions, but will have increased light-load power loss. If FCCM is forced low, the ISL62381, ISL62382 and ISL62383 will automatically operate in diode-emulationmode (DEM) at light load to optimize efficiency in the entire load range. The transition is automatically achieved by detecting the load current and turning off LGATE when the inductor current reaches 0A. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current flows into the drain of the low-side MOSFET. When the low-side MOSFET
MOSFET Gate-Drive Outputs LGATE and UGATE
The ISL62381, ISL62382 and ISL62383 have internal gate-drivers for the high-side and low-side N-Channel MOSFETs. The low-side gate-drivers are optimized for low duty-cycle applications where the low-side MOSFET conduction losses are dominant, requiring a low r DS(ON) MOSFET. The LGATE pull-down resistance is small in order
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conducts positive inductor current, the phase voltage will be negative with respect to the GND and PGND pins. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the GND and PGND pins. The ISL62381, ISL62382 and ISL62383 monitor the phase voltage when the low-side MOSFET is conducting inductor current to determine its direction. When the output load current is greater than or equal to 1/2 the inductor ripple current, the inductor current is always positive, and the converter is always in CCM. The ISL62381, ISL62382 and ISL62383 minimize the conduction loss in this condition by forcing the low-side MOSFET to operate as a synchronous rectifier. When the output load current is less than 1/2 the inductor ripple current, negative inductor current occurs. Sinking negative inductor current through the low-side MOSFET lowers efficiency through unnecessary conduction losses. The ISL62381, ISL62382 and ISL62383 automatically enter DEM after the PHASE pin has detected positive voltage and LGATE was allowed to go high for eight consecutive PWM switching cycles. The ISL62381, ISL62382 and ISL62383 will turn off the low-side MOSFET once the phase voltage turns positive, indicating negative inductor current. The ISL62381, ISL62382 and ISL62383 will return to CCM on the following cycle after the PHASE pin detects negative voltage, indicating that the body diode of the low-side MOSFET is conducting positive inductor current. Efficiency can be further improved with a reduction of unnecessary switching losses by reducing the PWM frequency. It is characteristic of the R3 architecture for the PWM frequency to decrease while in diode emulation. The extent of the frequency reduction is proportional to the reduction of load current. Upon entering DEM, the PWM frequency makes an initial step-reduction because of a 33% step-increase of the window voltage V W. Because the switching frequency in DEM is a function of load current, very light load conditions can produce frequencies well into the audio band. This can be problematic if audible noise is coupled into audio amplifier circuits. To prevent this from occurring, the ISL62381, ISL62382 and ISL62383 allow the user to float the FCCM input. This will allow DEM at light loads, but will prevent the switching frequency from going below ~28kHz to prevent noise injection into the audio band. A timer is reset each PWM pulse. If the timer exceeds 30s, LGATE is turned on, causing the ramp voltage to reduce until another UGATE is commanded by the voltage loop.
Overcurrent Protection
The overcurrent protection (OCP) setpoint is programmed with resistor, ROCSET, that is connected across the OCSET and PHASE pins.
L DCR PHASE1 + ROCSET + VROCSET RO ISEN1 VDCR CSEN _ IL _ CO VO
ISL62381
10A OCSET1
FIGURE 26. OVERCURRENT-SET CIRCUIT
Figure 26 shows the overcurrent-set circuit for SMPS1. The inductor consists of inductance L and the DC resistance (DCR). The inductor DC current IL creates a voltage drop across DCR, given by Equation 6:
V DCR = I L * DCR (EQ. 6)
The ISL62381, ISL62382 and ISL62383 sink a 10A current into the OCSET1 pin, creating a DC voltage drop across the resistor ROCSET, given by Equation 7:
V ROCSET = 10A * R OCSET (EQ. 7)
Resistor RO is connected between the ISEN1 pin and the actual output of the converter. During normal operation, the ISEN1 pin is a high impedance path, therefore there is no voltage drop across RO. The DC voltage difference between the OCSET1 pin and the ISEN1 pin can be established using Equation 8:
V OCSET1 - V ISEN1 = I L * DCR - 10A * R OCSET (EQ. 8)
The ISL62381, ISL62382 and ISL62383 monitor the OCSET1 pin and the ISEN1 pin voltages. Once the OCSET1 pin voltage is higher than the ISEN1 pin voltage for more than 10s, the ISL62381, ISL62382 and ISL62383 declare an OCP fault. The value of ROCSET is then written as Equation 9:
I OC * DCR R OCSET = -------------------------10A (EQ. 9)
Where: - ROCSET () is the resistor used to program the overcurrent setpoint - IOC is the output current threshold that will activate the OCP circuit - DCR is the inductor DC resistance For example, if IOC is 20A and DCR is 4.5m, the choice of ROCSET is ROCSET = 20A x 4.5m/10A = 9k.
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Resistor ROCSET and capacitor CSEN form an RC network to sense the inductor current. To sense the inductor current correctly, not only in DC operation but also during dynamic operation, the RC network time constant ROCSETCSEN needs to match the inductor time constant L/DCR. The value of CSEN is then written as Equation 10:
L C SEN = ----------------------------------------R OCSET * DCR (EQ. 10)
potentially damaging voltage levels. The LGATE gate-driver will turn off the low-side MOSFET once the FB pin voltage is lower than the falling overvoltage threshold for more than 2s. The falling overvoltage threshold is typically 106% of the reference voltage, or 1.06*0.6V = 0.636V. This process repeats as long as the output voltage fault is present, allowing the ISL62381/3 to protect against persistent over-voltage conditions. For ISL62382, if OVP is detected, it simply tri-states the PHASE node by turning UGATE and LGATE off.
For example, if L is 1.5H, DCR is 4.5m, and ROCSET is 9k, the choice of CSEN = 1.5H/(9k x 4.5m) = 0.037F. Upon converter start-up, the CSEN capacitor bias is 0V. To prevent false OCP during this time, a 10A current source flows out of the ISEN1 pin, generating a voltage drop on the RO resistor, which should be chosen to have the same resistance as ROCSET. When PGOOD pin goes high, the ISEN1 pin current source will be removed. When an OCP fault is declared, the PGOOD pin will pull-down to 32 and latch off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage, or until VIN has decayed below the falling POR threshold. When using a discrete current sense resistor, inductor time-constant matching is not required. Equation 7 remains unchanged, but Equation 8 is modified in Equation 11:
V OCSET1 - V ISEN1 = I L * R SENSE - 10A * R OCSET (EQ. 11)
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin voltage is below the undervoltage threshold for more than 2s. The undervoltage threshold is typically 86% of the reference voltage, or 0.86*0.6V = 0.516V. If a UVP fault is declared, and the PGOOD pin will pull-down with 93 and latch-off the converter. The fault will remain latched until the EN pin has been pulled below the falling enable threshold, or if VIN has decayed below the falling POR threshold.
Programming the Output Voltage
When the converter is in regulation there will be 0.6V between the FB and GND pins. Connect a two-resistor voltage divider across the OUT and GND pins with the output node connected to the FB pin as shown in Figure 27. Scale the voltage-divider network such that the FB pin is 0.6V with respect to the GND pin when the converter is regulating at the desired output voltage. The output voltage can be programmed from 0.6V to 5.5V. Programming the output voltage is written as Equation 13:
R TOP V OUT = V REF * 1 + ---------------------------- R BOTTOM (EQ. 13)
Furthermore, Equation 9 is changed in Equation 12:
I OC * R SENSE R OCSET = -----------------------------------10A (EQ. 12)
Where RSENSE is the series power resistor for sensing inductor current. For example, with an RSENSE = 1m and an OCP target of 10A, ROCSET = 1k.
Where: - VOUT is the desired output voltage of the converter - The voltage to which the converter regulates the FB pin is the VREF (0.6V) - RTOP is the voltage-programming resistor that connects from the FB pin to the converter output. In addition to setting the output voltage, this resistor is part of the loop compensation network - RBOTTOM is the voltage-programming resistor that connects from the FB pin to the GND pin Choose RTOP first when compensating the control loop, and then calculate RBOTTOM according to Equation 14:
V REF * R TOP R BOTTOM = -----------------------------------V OUT - V REF (EQ. 14)
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin voltage is above the rising overvoltage threshold for more than 2s. The FB pin voltage is 0.6V in normal operation. The rising over voltage threshold is typically 116% of that value, or 1.16*0.6V = 0.696V. When an OVP fault is declared, the PGOOD pin will pull down with 65 and latch-off the converter. The OVP fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage, or until VIN has decayed below the falling POR threshold. For ISL62381 and ISL62383, although the converter has latched-off in response to an OVP fault, the LGATE gatedriver output will retain the ability to toggle the low-side MOSFET on and off in response to the output voltage transversing the OVP rising and falling thresholds. The LGATE gate-driver will turn on the low-side MOSFET to discharge the output voltage, thus protecting the load from
Compensation Design
Figure 27shows the recommended Type-II compensation circuit. The FB pin is the inverting input of the error amplifier. The COMP signal, the output of the error amplifier, is inside the chip and unavailable to users. CINT is a 100pF capacitor integrated inside the IC that connects across the FB pin and the
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COMP signal. RTOP, RFB, CFB and CINT form the Type-II compensator. The frequency domain transfer function is given by Equation15:
1 + s * ( R TOP + R FB ) * C FB G COMP ( s ) = ------------------------------------------------------------------------------------------s * R TOP * C INT * ( 1 + s * R FB * C )
FB
a voltage greater than the LDO3 output voltage plus the dropout voltage. Currents in excess of the limit will cause the LDO3 voltage to drop dramatically, limiting the power dissipation.
(EQ. 15)
Thermal Monitor and Protection
LDO3 and LDO5 can dissipate non-trivial power inside the ISL62381, ISL62382 and ISL62383 at high input-to-output voltage ratios and full load conditions. To protect the silicon, ISL62381, ISL62382 and ISL62383 continually monitor the die temperature. If the temperature exceeds +150C, all outputs will be turned off to sharply curtail power dissipation. The outputs will remain off until the junction temperature has fallen below +135C.
CINT = 100pF
RFB
CFB
RTOP
-
VO FB RBOTTOM
EA COMP
+
REF ISL6238
General Application Design Guide
This design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following section. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts.
FIGURE 27. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency that causes rapid phase change. The R3 modulator used in the ISL62381, ISL62382 and ISL62383 make the LC output filter resemble a first order system in which the closed loop stability can be achieved with the recommended Type-II compensation network. Intersil provides a PC-based tool (example page is shown later) that can be used to calculate compensation network component values and help simulate the loop frequency response.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the input and the output voltage. This relationship is written as Equation 17:
V OUT D = -------------V IN (EQ. 17)
LDO5 Linear Regulator
In addition to the two SMPS outputs, the ISL62381, ISL62382 and ISL62383 also provide two linear regulator outputs. LDO5 is fixed 5V LDO output capable of sourcing 100mA continuous current. When the output of SMPS2 is programmed to 5V, SMPS2 will automatically take over the load of LDO5. This provides a large power savings and boosts the efficiency. After switchover to SMPS2, the LDO5 output current plus the MOSFET drive current should not exceed 100mA in order to gurarantee the LDO5 output voltage in the range of 5V 5%. The total MOSFET drive current can be estimated by Equation 16.
I DRIVE = Q g F SW (EQ. 16)
The output inductor peak-to-peak ripple current is written as Equation 18:
V OUT * ( 1 - D ) I PP = ------------------------------------F SW * L (EQ. 18)
A typical step-down DC/DC converter will have an IP-P of 20% to 40% of the maximum DC output load current. The value of IP-P is selected based upon several criteria such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. The DC copper loss of the inductor can be estimated by Equation 19:
P COPPER = I LOAD
2
*
DCR
(EQ. 19)
Where ILOAD is the converter output DC current. The copper loss can be significant so attention has to be given to the DCR selection. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperatures. A saturated inductor could cause destruction of circuit components, as well as nuisance OCP faults. A DC/DC buck regulator must have output capacitance CO into which ripple current IP-P can flow. Current IP-P develops out of the capacitor. These two voltages are written as Equation 20:
V ESR = I PP * E SR (EQ. 20)
where Qg is the total gate charge of all the power MOSFET in two SMPS regulators. Then the LDO5 output load current should be less than 100mA-IDRIVE.
LDO3 Linear Regulator
ISL62381, ISL62382 includes LDO3 linear regulator whose output is adjustable from 1.2V to 5V through LDO3FB pin with a 1.2V reference voltage. It can be independently enabled from both SMPS channels. Logic high of LDO3EN will enable LDO3. LDO3 is capable of sourcing 100mA continuous current and draws its power from LDO3IN pin, which must be connected to
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NORMALIZED INPUT RMS RIPPLE CURRENT
and Equation 21:
I PP V C = ------------------------------8 * CO * F
SW
0.6
(EQ. 21)
0.48
If the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total ESR until the required VP-P is achieved. The inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors should be considered in this scenario. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that IP-P is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at FSW. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases.
0.36
0.24
k=1 k = 0.75 k = 0.5 k = 0.25 k=0
0.12
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
DUTY CYCLE
FIGURE 28. NORMALIZED RMS INPUT CURRENT @ EFF = 1
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. Figure 28 is a graph of the input capacitor RMS ripple current, normalized relative to output load current, as a function of duty cycle and is adjusted for converter efficiency. The normalized RMS ripple current calculation is written as Equation 22:
Dk I MAX D ( 1 - D ) + -------------12 I C ( RMS ,NORMALIZED ) = ---------------------------------------------------------------------I MAX IN (EQ. 22)
2
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET switches off. There are several power MOSFETs readily available that are optimized for DC/DC converter applications. The preferred high-side MOSFET emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. Unlike the low-side MOSFET which has the drain-source voltage clamped by its body diode during turn off, the high-side MOSFET turns off with a VDS of approximately VIN - VOUT, plus the spike across it. The preferred low-side MOSFET emphasizes low r DS(ON) when fully saturated to minimize conduction loss. It should be noted that this is an optimal configuration of MOSFET selection for low duty cycle applications (D < 50%). For higher output, low input voltage solutions, a more balanced MOSFET selection for high- and low-side devices may be warranted. For the low-side (LS) MOSFET, the power loss can be assumed to be conductive only and is written as Equation 24:
P CON_LS I LOAD r DS ( ON )_LS * ( 1 - D )
2
Where: - IMAX is the maximum continuous ILOAD of the converter - k is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as:
V OUT D = ------------------------V IN EFF (EQ. 23)
(EQ. 24)
In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET.
For the high-side (HS) MOSFET, the its conduction loss is written as Equation 25:
P CON_HS = I LOAD
2
*
r DS ( ON )_HS * D
(EQ. 25)
For the high-side MOSFET, the switching loss is written as Equation 26:
V IN * I PEAK * t OFF * f V IN * I VALLEY * t ON * f SW SW P SW_HS = ---------------------------------------------------------------- + -----------------------------------------------------------2 2 (EQ. 26)
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Where: - IVALLEY is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current - IPEAK is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current - tON is the time required to drive the device into saturation - tOFF is the time required to drive the device into cut-off
Co
Pin 4 (VCC2) Pin 21 (VIN)
L2
L2 U2
ISL62381 and ISL62382 line of symmetry
Ci
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as Equation 27:
Qg C BOOT = ----------------------V BOOT (EQ. 27)
PGND Plane PHASE Planes VOUT Planes VIN Plane
Ci
L1 U1
L1 Co
Where: - Qg is the total gate charge required to turn on the high-side MOSFET - VBOOT, is the maximum allowed voltage decay across the boot capacitor each time the high-side MOSFET is switched on As an example, suppose the high-side MOSFET has a total gate charge Qg, of 25nC at VGS = 5V, and a VBOOT of 200mV. The calculated bootstrap capacitance is 0.125F; for a comfortable margin, select a capacitor that is double the calculated capacitance. In this example, 0.22F will suffice. Use an X7R or X5R ceramic capacitor.
FIGURE 30. SYMMETRIC LAYOUT GUIDE
Signal Ground and Power Ground
The bottom of the ISL62381, ISL62382 and ISL62383 TQFN package is the signal ground (GND) terminal for analog and logic signals of the IC. Connect the GND pad of the ISL62381, ISL62382 and ISL62383 to the island of ground plane under the top layer using several vias for a robust thermal and electrical conduction path. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground (PGND) plane. The following pin descriptions take ISL62381 and ISL62382 as an example. PGND (Pin 23) This is the return path for the pull-down of the LGATE low-side MOSFET gate driver. Ideally, PGND should be connected to the source of the low-side MOSFET with a low-resistance, low-inductance path. VIN (Pin 21) The VIN pin should be connected close to the drain of the high-side MOSFET, using a low resistance and low inductance path. VCC (Pins 4 and 5) For best performance, place the decoupling capacitor very close to the VCC and GND pins. LDO5 (Pin 22) For best performance, place the decoupling capacitor very close to the LDO5 and respective PGND pin, preferably on the same side of the PCB as the ISL6238 IC. EN (Pins 13 and 28) and PGOOD (Pins 1 and 8) These are logic signals that are referenced to the GND pin. Treat as a typical logic signal. OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30) For DCR current sensing, current-sense network, consisting of ROCSET and CSEN, needs to be connected to the
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Layout Considerations
As a general rule, power should be on the bottom layer of the PCB and weak analog or logic signals are on the top layer of the PCB. The ground-plane layer should be adjacent to the top layer to provide shielding. The ground plane layer should have an island located under the IC, the compensation components, and the FSET components. The island should be connected to the rest of the ground plane layer at one point.
VIAS TO VIAS TO GROUND GROUND PLANE PLANE
GND
OUTPUT OUTPUT CAPACITORS CAPACITORS SCHOTTKY SCHOTTKY DIODE DIODE LOW-SIDE LOW-SIDE MOSFETS MOSFETS INPUT INPUT CAPACITORS CAPACITORS
VOUT
INDUCTOR INDUCTOR
PHASE NODE
HIGH-SIDE HIGH-SIDE MOSFETS MOSFETS
VIN
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
Because there are two SMPS outputs and only one PGND pin, the power train of both channels should be layed out symmetrically. The line of bilateral symmetry should be drawn through pins 4 and 21 (pins 4 and 18 for ISL62383). This layout approach ensures that the controller does not favor one channel over another during critical switching decisions. Figure 30 illustrates one example of how to achieve proper bilateral symmetry. 20
ISL62381, ISL62382, ISL62383
inductor pads for accurate measurement. Connect ROCSET to the phase-node side pad of the inductor, and connect CSEN to the output side pad of the inductor. The ISEN resistor should also be connected to the output pad of the inductor with a separate trace. Connect the OCSET pin to the common node of node of ROCSET and CSEN. For resistive current sensing, connect ROCSET from the OCSET pin to the inductor side of the resistor pad. The ISEN resistor should be connected to the VOUT side of the resistor pad. In both current-sense configurations, the resistor and capacitor sensing elements, with the exclusion of the current sense power resistor, should be placed near the corresponding IC pin. The trace connections to the inductor or sensing resistor should be treated as Kelvin connections. FB (Pins 9 and 32), and VOUT (Pins 10 and 31) The VOUT pin is used to generate the R3 synthetic ramp voltage and for soft-discharge of the output voltage during shutdown events. This signal should be routed as close to the regulation point as possible. The input impedance of the FB pin is high, so place the voltage programming and loop compensation components close to the VOUT, FB, and GND pins keeping the high impedance trace short. FSET (Pins 2 and 7) These pins require a quiet environment. The resistor RFSET and capacitor CFSET should be placed directly adjacent to these pins. Keep fast moving nodes away from these pins. LGATE (Pins 17 and 24) The signal going through these traces are both high dv/dt and high di/dt, with high peak charging and discharging current. Route these traces in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces. There should be no other weak signal traces in proximity with these traces on any layer. BOOT (Pins 16 and 25), UGATE (Pins 15 and 26), and PHASE (Pins 14 and 27) The signals going through these traces are both high dv/dt and high di/dt, with high peak charging and discharging current. Route the UGATE and PHASE pins in parallel with short and wide traces. There should be no other weak signal traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the upper MOSFET and the source of the lower MOSFET to suppress the turn-off voltage spike.
21
FN6665.4 August 7, 2008
ISL62381, ISL62382, ISL62383
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 9/06
4 . 00 PIN 1 INDEX AREA A 2 . 50 B 0 . 40 22 21 28 PIN #1 INDEX AREA CHAMFER 0 . 400 X 45
1 0 . 4 x 6 = 2.40 REF
4 . 00
2 . 50
0 . 40
15 0 . 10 2X 14 8
7
0 . 20 0 . 05
TOP VIEW
0 . 4 x 6 = 2 . 40 REF 3 . 20
0 . 10 M C A B
BOTTOM VIEW
SEE DETAIL X'' (3 . 20) PACKAGE BOUNDARY MAX. 0 . 80 SEATING PLANE (28X 0 . 20) 0 . 00 - 0 . 05 0 . 20 REF 0 . 08 C 0 . 10 C C
SIDE VIEW
(2 . 50) (3 . 20)
(0 . 40) C
0 . 20 REF
5
(0 . 40) (2 . 50) (28X 0 . 60)
0 ~ 0 . 05
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Controlling dimensions are in mm. Dimensions in ( ) for reference only. 2. Unless otherwise specified, tolerance : Decimal 0.05 Angular 2 3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994. 4. Bottom side Pin#1 ID is diepad chamfer as shown. 5. Tiebar shown (if present) is a non-functional feature.
22
FN6665.4 August 7, 2008
3 . 20
ISL62381, ISL62382, ISL62383 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
2X A D D/2 0.15 C A
L32.5x5A
32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) MILLIMETERS SYMBOL
2X
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A
0.15 C B
6 INDEX AREA
N 1 2 3 E/2 E
A1 A3 b D D2 E
0.18
0.25 5.00 BSC
0.30
5, 8 -
3.30
3.45 5.00 BSC 5.75 BSC
3.55
7, 8 9
TOP VIEW
B
E1 E2 e
A
3.30
3.45 0.50 BSC
3.55
7, 8 -
k
/ / 0.10 C 0.08 C
0.20 0.30
0.40 32 8 8
0.50
8 2 3 3 Rev. 2 05/06
C
L N Nd Ne
SEATING PLANE
SIDE VIEW
A3
A1
NX b D2 D2 2
5 0.10 M C A B 7 8 NX k N
(DATUM B)
(DATUM A) (Ne-1)Xe REF. 8
6 INDEX AREA
E2 3 2 1 NX L N 8 e (Nd-1)Xe REF. BOTTOM VIEW E2/2
7
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
A1 NX b 5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 23
FN6665.4 August 7, 2008

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